1. Field of the Invention
The present invention relates to communication systems. More specifically, the present invention relates to data encryption and decryption devices used in secure communication systems.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
2. Description of the Related Art
Numerous data encryption and decryption schemes are known and used in the art to protect "secure" voice and data communication channels from unauthorized intrusion and detection. Encryptors implement frequency hopping, spread spectrum and other schemes to secure the communications link.
Encryption and decryption typically involve the use of a sequence generator to provide a random or pseudorandom sequence of data bits which are used to control the frequency hopping, spectrum spreading or other security scheme of the system.
Sequence generators generally include a random data source the output of which is gated into a shift register as some function of the data stored therein. A switch is activated by control logic. Through the switch, the control logic clocks random data into the shift register, in accordance with the random data bit rate, until a given number of random bit words have been input. At this point, the switch is activated and a function of the random data bits stored in the shift register is fed back to the shift register through the switch. This feedback also constitutes the output of the sequence generator. The output sequence is used to encrypt/decrypt data in a transmitter/receiver or used to control the frequency hopping, spectrum spreading or other security scheme thereof.
For improved security, the state of the encryptor should be "randomized" prior to use. Randomization is typically achieved with a random bit stream from the external, low rate, random data source to establish a random state starting point within the sequence generator.
Unfortunately, the speed of the sequence generator is currently limited by the rate at which the random data source outputs random bits, a rate which is generally substantially lower than the clock rate of the processor in the control logic. As a result, the sequence generator must be slowed to a rate appropriate for the random data source. Two methods are currently used to disable the sequence generator: 1) either the system clock is slowed or 2) the shift register is disabled.
Clock disabling or gating is considered to be a poor design practice due to the multitude of timing and test problems which can be created. Improper timing resulting from the use of gated clock signals can generate a false clock signal and cause a flip-flop to clock in incorrect data.
In addition to improper timing problems, the use of gated clock signals can cause problems for the scan chain based testing and fault grading techniques widely applied in current VLSI design.
The second method of slowing the sequence generator involves the addition of a hold mode to every flip-flop within the shift register of the sequence generator. The shift register includes a series of flip-flops. When implemented without a disable mode, the output of one flip-flop is input to the next and a high operational speed is achieved. When implemented with a disable mode, a 2:1 multiplexer is added to the input of each flip-flop. One multiplexer input is driven by the line that would normally connect to the flip-flop input while the other multiplexer input is driven the flip-flop output. The output of the multiplexer is connected to the flip-flop input. Each of the multiplexers is controlled by a common, high fan out "enable" or "disable" signal. While feasible for moderate speed designs, this approach is unacceptable for high speed designs. Multiplexers add delay to critical paths and reduce maximum operational speeds. High speed, high fan out signals are difficult to implement. The additional gates required for multiplexers and for the disable control distribution increase device sizes which reduces device speed.
Thus, although adding a disable mode to the sequence generator is a more acceptable design approach, this approach increases gate/parts counts, increases power consumption, increases device complexity, adds delay to critical paths within the sequence generator, and thereby reduces performance limits.
Accordingly, there is a need in the art for a technique for achieving randomization of encryptor systems without suffering the performance degradation normally associated with a disabling of the system clock or the shift register of the sequence generator.